Integrated circuits use dielectric layers, which have typically been formed from silicon dioxide, SiO2, to insulate conductive lines on various layers of a semiconductor structure. As semiconductor circuits become faster and more compact, operating frequencies increase and the distances between the conductive lines within the semiconductor device decrease. This introduces an increased level of coupling capacitance to the circuit, which has the drawback of slowing the operation of the semiconductor device. Therefore, it has become important to use dielectric layers that are capable of effectively insulating conductive lines against such increasing coupling capacitance levels.
In general, the coupling capacitance in an integrated circuit is directly proportional to the dielectric constant of the material used to form the dielectric layers. As noted above, the dielectric layers in conventional integrated circuits have traditionally been formed of SiO2, which has a dielectric constant of about 4.0. As a consequence of the increasing line densities and operating frequencies in semiconductor devices, dielectric layers formed of SiO2 may not effectively insulate the conductive lines to the extent required to avoid increased coupling capacitance levels.
In an effort to reduce the coupling capacitance levels in integrated circuits, the semiconductor industry has engaged in research to develop materials having a dielectric constant lower than that of SiO2, which materials are suitable for use in forming the dielectric layers in integrated circuits. To date, a number of promising materials, which are sometimes referred to as “low-k materials”, have been developed. Many of these new dielectrics are organic compounds. In the specification and claims, a low-k material is defined as a material with a dielectric constant “k” that is less than 3.
Low-k materials include, but are specifically not limited to: benzocyclobutene or BCB; Flare™ manufactured by Allied Signal® of Morristown, N.J., a division of Honeywell, Inc., Minneapolis, Minn.; one or more of the Parylene dimers available from Union Carbide® Corporation, Danbury Conn.; polytetrafluoroethylene or PTFE; and SiLK®. One PTFE suitable for IC dielectric application is SPEEDFILM™, available from W. L. Gore & Associates, Inc, Newark, Del. SiLK®, available from the Dow® Chemical Company, Midland, Mich., is a silicon-free BCB.
During semiconductor wafer processing, features of the semiconductor device are defined in the wafer using well-known patterning and etching processes. In these processes a photoresist (PR) material is deposited on the wafer and then is exposed to light filtered by a reticle. The reticle is generally a glass plate that is patterned with exemplary feature geometries that blocked light from propagating through the reticle.
After passing through the reticle, the light contacts the surface of the photoresist material. The light changes the chemical composition of the photoresist material such that a developer can remove a portion of the photoresist material. In the case of positive photoresist materials the exposed regions are removed, and in the case of negative photoresist materials the unexposed regions are removed. Thereafter the wafer is etched to remove the underlying material from the areas that are no longer protected by the photoresist material and thereby define the desired features in the wafer. Low-K organic polymers in general can be etched by oxidation (e.g. oxygen-based) or reduction (e.g. hydrogen-based) chemical processes.
The etching of dielectrics may be advantageously accomplished in a dual-frequency capacitively-coupled, (DFC) dielectric etch system. One such is Lam® Research model 4520XLE™ and Exelan-HP™, available from Lam® Research Corporation, Fremont Calif. The 4520XLE™ system processes an extremely comprehensive dielectric etch portfolio in one system. Processes include contacts and vias, bilevel contacts, borderless contacts, nitride and oxide spacers, and passivation.
Advanced etch systems like the 4520XLE™ perform several processes in the same system. By performing many different semiconductor fabrication steps in a single system, wafer throughput can be increased. Even further advanced systems contemplate the performance of additional steps within the same equipment. Again by way of example, but not limitation, Lam® Research Corporation's Exelan™ system is a dry etch system capable of performing many process steps in a single apparatus. Exelan™ enables hardmask open, inorganic and organic ARC etch, and photoresist strip to be performed in situ with a single chamber. This system's extensive process portfolio includes all dual damascene structures, contacts, vias, spacers, and passivation etch in doped and undoped oxides and low-k dielectrics required in the sub-0.18 micron environment. Of course, the principles enumerated herein may be implemented in wide variety of semiconductor fabrication systems, and these principles specifically contemplate all such alternatives.
As used herein, the term in situ refers to one or more processes performed on a given substrate, such as a silicon wafer, in the same piece of semiconductor fabrication equipment without removing the substrate from the equipment.
Many current integrated circuit fabrication technologies utilize a photoresist stripping step following one or more of the patterning steps used to form the features in the wafer. Because many photoresists have similar chemical compositions with respect to low-k dielectrics, especially organic low-k dielectrics, such as SiLK, in order to ensure good profile control during the etching of a feature in a wafer, a hard mask is often employed beneath the photoresist.
An example wafer stack incorporating a hard mask layer is shown at FIG. 1a. The wafer, 1, having a patterned layer of photoresist, 10, is shown. In this example, wafer 1 includes a silicon substrate, 22 having deposited thereon a silicon carbide or silicon nitride barrier layer, 20. Deposited over barrier layer 20 is a layer 14 of an organic low-k dielectric, for instance Dow Corning Silk™. A metalized structure, not shown, may be formed under the barrier layer. A hard mask layer is deposited over organic low-k layer 14, completing the exemplar wafer stack. Hard mask may be formed of SiO2, Si3N4, or other hard mask materials. Patterned photoresist layer 10, previously discussed, is applied over hard mask 12. Of course, it will be recognized by those having skill in the art that this wafer stack is exemplary only. Alternative structures and films, known to those having skill in the art may be utilized to implement alternative integrated circuit designs.
Having reference now to FIG. 1b, as etching proceeds, especially the etching of the organic low-k dielectric layer, such as SiLK, as shown in FIG. 1b, photoresist layer 10 is etched away, exposing portions of hard mask layer 12, beneath. As etching continues, ion bombardment of the hard mask layer also etches away a portion of hard mask layer 12, for instance at 30. Some of the hard mask material so etched away is re-deposited, for instance by sputtering, on surfaces of the wafer and may also be re-deposited on surfaces of the reaction chamber. At least some of this material, 32, is further deposited at the bottom of etched features during etching, as shown at 36, and in section “A”. The amount of micromasking increases with increased RF power during etching.
Section “A” is enlarged at FIG. 1c. With reference to that figure, a feature, for instance 26, is shown being etched through the organic low-k dielectric layer 14, such as SiLK. The hard mask material re-deposited at 36 is seen in photomicrographs to form spicules 34 of hard mask material. The visual appearance of this material gives rise to one nickname therefor: “grass”, and it is the sputtered hard mask that micromasks the SiLK, which forms the “grass”. The micromask of course not only slows the etch rate of the feature, but it can render the etching of the feature erratic and irregular, leading in extreme cases to poor profile control and yield reduction.
What is desirable is a methodology which mitigates, and preferably eliminates the formation of grass during etching of features in integrated circuits while maintaining CD (critical dimension) control during that etching.
What is further desirable is that the process be capable of providing good profile control during etching by providing sidewall passivation, minimizing lateral etching of the organic low-k material. The methodology should enable vertical to positively sloped features in organic low-k materials.
What is further desirable is a process which could reduce the unwanted erosion of photoresist during etching.
What is further desirable is a process, which could protect the hard mask once it is exposed to the plasma due to the clearing of the photoresist.
What is also desirable is a methodology which is functional across a broad range of etch plasma densities.
In order to facilitate further wafer processing and overall device quality, it is desirable that the methodology provide residue-free surfaces.
In order to maintain a high wafer throughput, what is also desirable is that the methodology be capable of being performed in situ within the fabrication equipment utilized to form the wafer.
Finally, it would be very desirable if the these advantages could be implemented using existing integrated circuit manufacturing equipment.
These and other features of the present invention will be described in more detail in the section entitled detailed description of the preferred embodiments and in conjunction with the following figures.